1. Field of the Invention
The present invention relates to a data processing system for use in the processing of single-precision data such as 32-bit floating-point representation data and double-precision data such as 64-bit floating-point representation data.
2. Description of the Related Art
Recently, as the amount of data processed in computers having a high functionality and high performance is increased, there is a growing need to effectively carry out the processing of logic calculations and arithmetic calculations, such as scientific calculations, at a high speed. Accordingly, vector processors are used to process single-precision data and double-precision data through pipelines such as an add pipeline, a multiply pipeline, and a division pipeline.
In a prior art vector processor, a double-precision operation unit such as an adder unit also processes single-precision data. To accomplish this, in a single-precision operation mode, a single-precision data to double-precision data conversion unit and a double-precision data to single-precision data conversion unit are connected to a prestage and a poststage of the double-precision operation unit, respectively, as will be later explained in more detail.
In the above-mentioned prior art vector processor, however, a space (or unused memory area) is generated in the memory region of the vector registers, and double-precision transmission lines between the vector registers and the double-precision operation unit.
Also, in the above-mentioned prior art vector processor, it is possible to transmit two single-precision data through the double-precision transmission lines, to the double-precision operation unit. In this case, however, since only one single-precision data can be processed by the double-precision operation unit, the processing of the other single-precision data must be delayed until processing of the first single-precision data is completed, which is an obstacle to an enhancing of the operation speed.